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Archive for September, 2011

Intel Ivy Bridge at IDF 2011

Varghese George, senior principal engineer, has detailed information on the upcoming Ivy Bridge microarchitecture that’s due to be released in 1H 2012.

Ivy Bridge is the successor to incumbent Sandy Bridge – the design which powers the majority of Intel’s silicon available today – and it’s considered a tick in Intel’s nomenclature.

Ivy’s central core design is similar to Sandy Bridge in some ways, George said, as it features the same two-chip solution – PCH and CPU – socket, shared cache, and memory-controller found on the incumbent chip.

But George went on to explain that shifting down to 22nm and using the new-fangled tri-gate transistors enables Intel to offer either greater power efficiency or more performance than Sandy Bridge for a set die size, though he would not divulge actual numbers at the technical seminar at IDF.

While performance is clearly important for an architecture that’ll scale from ultra-low-voltage laptops through to servers, George was keen to point out that many of the improvements in Ivy Bridge relate to power efficiency. For example, new power-management features enable more-granular control over the chips’ cores and voltages, extending through to particular chips having multiple TDP settings that can be dynamically adjusted by a PC-manufacturing partner – a range of power settings on one chip, if you will. This intriguing notion was glossed over somewhat, and we plan to learn more tomorrow.