Pegatron IPMSB-GS S1155 H67/DVI-HDMI/USB3/µATX, Unlocked Bios or ...?

[Bitseeker]

IPMSB-GS-0400.ROM consists of ME region (2Mb) + BIOS region (2Mb).
AMIBOOT.ROM is used for BIOS recovery.

Ah, thx...

OK, i will flash ... back in few min... i hope

[Bitseeker]

Hi,

flash not work, now ERROR 25: "PDR REGION DOES NOT EXIST" :/




Well, i have no more Time yet, if you can and will, please write further any Solutions, i will read later and try :
Thank you so much!!

[DeathBringer]

Try AFUEFI in zip-file AFUEFI2_36.zip
AFUEFI IPMSB-GS-0400.ROM /p /b /n /r

[DeathBringer]

1. Take USB stick and format to FAT32
2. Create directory structure EFI\Boot
3. Download and unzip bootx64.7z
4. Put BOOTX64.EFI to Boot directory.
5. Boot from this USB stick
6. Run command: setup_var 0x22
7. Make and post foto of the screen.

[Bitseeker]

[censored] Yeah,

flash has work, THX !!

But, nothing changed in Biosstructure (no Jumperfree or other Settings, all Same as old Version), just Bios Version from 0212 to 4.00
I dont know, what the different between Bios 0212 and 4.00?

now i must hurry up.... later more
Will do then steps 1 to 7

Here Coreinfo after flash:

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright © 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

Intel® Core™ i5-2320 CPU @ 3.00GHz
Intel64 Family 6 Model 42 Stepping 7, GenuineIntel
Microcode signature: 00000029
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
EPT * Supports Intel extended page tables (SLAT)

c:\>coreinfo

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright © 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

Intel® Core™ i5-2320 CPU @ 3.00GHz
Intel64 Family 6 Model 42 Stepping 7, GenuineIntel
Microcode signature: 00000029
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode

SMX - Supports Intel trusted execution
SKINIT - Supports AMD SKINIT

NX * Supports no-execute page protection
SMEP - Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB - Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE - Supports direct GS/FS base access

FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2

AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA - Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND - Supports RDRAND instruction
RDSEED - Supports RDSEED instruction

CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 - Supports bit manipulation extensions 1
BMI2 - Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA - Supports prefetch from memory-mapped device
F16C - Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE - Supports MOVBE instruction
ERMSB - Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT - Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions

DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID - Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages

EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC - Supports x2APIC

CNXT-ID - L1 data cache mode adaptive or BIOS

MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin

PSN - Implements 96-bit processor serial number

PREFETCHW * Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 80000008 (Extended).

Logical to Physical Processor Map:
*--- Physical Processor 0
-*-- Physical Processor 1
--*- Physical Processor 2
---* Physical Processor 3

Logical Processor to Socket Map:
**** Socket 0

Logical Processor to NUMA Node Map:
**** NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*--- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
*--- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
*--- Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**** Unified Cache 1, Level 3, 6 MB, Assoc 12, LineSize 64
-*-- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
-*-- Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
--*- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
--*- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
--*- Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
---* Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
---* Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
---* Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64

Logical Processor to Group Map:
**** Group 0

[DeathBringer]

Will do then steps 1 to 7

I need it to enable Turbo.

[Bitseeker]

Hi,

i'm back

Well don't work with EFI Boot, my Bios seems like not a UEFI Bios, just normal Bios, nothing to set Secure Boot or other UEFI functions.

Stick wont Boot, "No OS found to Boot, try another Drive blahblahblah" :/

BTW: Give anywhere Changelog too from Biosversion 4.00, which CPUs are now supported or RAMs or???

Well i can load Rom to Ami Aptio UEFI MMTool, but NOT with NON UEFI MMTOOL o.O , just, i don't know, what i can do with this Tool

[DeathBringer]

Your motherboard hasn't any memory controller, but CPU has. So maximum of memory is determined by CPU. i5-2320 supports 32 GB.
Almost all DIMM DDR3 with 1600 Mhz can be used in your motherboard on 1333 Mhz speed (automatically).
All CPU with Sandy Bridge core are supported, but Ivy Bridge are not.

To enable Turbo Boost:
1. Download AMIBCP v4.53 or v4.55.
2. Open IPMSB-GS-0400.ROM with it.
3. Go to Main->Advanced->CPU Configuration.
4. Change Turbo Boost Tech for Optimal to Enable.
5. Save and reflash BIOS.

[DeathBringer]

BTW: Did you change FLASH OVERRIDE jumper before BIOS flashing?
IPMSB-GS manual

[Bitseeker]

BTW: Did you change FLASH OVERRIDE jumper before BIOS flashing?
IPMSB-GS manual

No, was default, may i should?

Have now modified Rom and flashed, Turboboost is now active in Bios :
THX for your patience :