[REQUEST] DELL Dimension 9200 / XPS410 Microcode Update

[CKY]

Those are going to be some mighty small pieces of tape, especially for the pins on the inner rows. And keeping them in place while socketing the CPU would be challenging. I think the task exceeds my level of incompetence.

[DeathBringer]

Those are going to be some mighty small pieces of tape, especially for the pins on the inner rows.

You can isolate L1 & L2, P1, T1 & T2.

[CKY]

Those are going to be some mighty small pieces of tape, especially for the pins on the inner rows.

You can isolate L1 & L2, P1, T1 & T2.

I understand your approach now; sorta like the mod stickers for adapting a Xeon LGA 771 CPU to a 775 socket.  Still, mighty close tolerances involved to get the placement just right and avoid masking adjacent pins.

[DeathBringer]

Without pads isolating the last chance is E7300 or E7500.

[CKY]

Without pads isolating the last chance is E7300 or E7500.

Have E7500 on order.  Will post test results.

I'm not optimistic tho. As I understand it, the base clock will still be 266 and whether the CPU uses an integer or fractional multiplier is a CPU internal setting and should not matter. It is interesting that every one of the Conroe CPUs has an integer multiplier. I'm ignorant of BIOS structure, but I suppose that the CPU internal multiplier setting could be fed back to the BIOS and cause it to hang if it gets a number it can't handle. I came across an old blog where users had Wolfdale processors working with an MSI motherboard based on the P965 chipset. From that, I would conclude that Dell's hardware implementation may be the showstopper.

[CKY]

FAILED with E7500 and latest modified BIOS.     Will conclude that a hardware limitation prevents use of 45nm Wolfdale CPUs.

[William P]

The XPS 410,9200, and E520 all share the same MB layout. The PLL is locked to 266FSB. This is done by a .7 Volt TME latching input signal to PLL pin 4 during POST. The pin them becomes a PCI output frequency. This prevents spoofing it with a pull down resistor. It might be possible to hex edit this setting in SetFSB, or RW Everything. This also blocks SetFSB, and pinmods from working.
The 45nm Core2 CPUs use VID11, the 65nm use VID10 Voltage table. So VID pinout is different.
You can run a QX6800 SLACP and overclock it with Throttlestop 6.00 software in Windows to as much as 4GHz. This gives control of multiplier, and voltage.The Multiplier steps ARE whole integers. This doesn't answer the question as it was asked, but does provide another approach to improving the performance of these systems. Heatsinking the VRM MOSFETs, and removing the fan power from the MB header help a lot.

[DeathBringer]

The 45nm Core2 CPUs use VID11, the 65nm use VID10 Voltage table. So VID pinout is different.

You are wrong. Read datasheets.

[William P]

That's where I got it from. I may have stated it imprecisely but there is one VID table that use VID 0-6, and a different one for some newer CPUs that uses VID 0-7. Exactly when they switched and which CPUs use which I guess I'm not sure. It's something to take into consideration when trying to swap CPUs.
https://www.manualslib.com/manual/550916...=17#manual
https://www.intel.com/content/dam/www/pu...asheet.pdf

Also there are 2 more motherboards related to these. the Dimension 9200c, and the XPS210, both USFF versions.

[DeathBringer]

VID7 and VID0 are not used. They are always strapped to Vss.