Forum RSS Feed Follow @ Twitter Follow @ Twitter

Thread Rating:
  • 0 Vote(s) - 0 Average
  • 1
  • 2
  • 3
  • 4
  • 5
SST25VF080B Firmware Chip
#1
8 Mbit SPI Serial Flash
SST25VF080B
FEATURES:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 50 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 μA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 μs (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (6mm x 5mm)
• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION
SST’s 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. The SST25VF080B devices are
enhanced with improved operating frequency and even
lower power consumption than the original SST25VFxxxA
devices. SST25VF080B SPI serial flash memories are
manufactured with SST’s proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.

The SST25VF080B devices significantly improve performance
and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
supply of 2.7-3.6V for SST25VF080B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The SST25VF080B device is offered in both 8-lead SOIC
(200 mils) and 8-contact WSON (6mm x 5mm) packages.
See Figure 1 for pin assignments.

[Image: SST_A.jpg]

[Image: SST_B.jpg]

MEMORY ORGANIZATION
The SST25VF080B SuperFlash memory array is organized
in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
DEVICE OPERATION
The SST25VF080B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to

select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF080B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 2, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.

[Image: SST_C.jpg]

Hold Operation
The HOLD# pin is used to pause a serial sequence underway
with the SPI flash memory without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be
in active low state. The HOLD# mode begins when the
SCK active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not

coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 3 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in highimpedance
state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
23 for Hold timing.

[Image: SST_D.jpg]

[Image: SST_E.jpg]

Write Protection
SST25VF080B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register provide
Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function
of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down function
of the BPL bit is disabled.

Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of
the Memory Write protection. During an internal Erase or

Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 3 describes the function of each bit in the software
status register.

[Image: SST_F.jpg]

Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically
reset under the following conditions:
• Power-up
• Write-Disable (WRDI) instruction completion
• Byte-Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector-Erase instruction completion
• Block-Erase instruction completion
• Chip-Erase instruction completion
• Write-Status-Register instructions

Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit provides
status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.

Block Protection (BP3,BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as defined in Table 4, to be software
protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if Block-
Protection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to 1.

Block Protection Lock-Down (BPL)
WP# pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (VIH), the BPL bit has no
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.

[Image: SST_G.jpg]

Instructions
Instructions are used to read, write (Erase and Program),
and configure the SST25VF080B. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, Write-Status-Register, or Chip-Erase instructions,
the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in
Table 5. All instructions are synchronized off a high to low
transition of CE#. Inputs will be accepted on the rising edge

of SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low to high transition on CE#,
before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device
to standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.

[Image: SST_H.jpg]

Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high transition
on CE#. The internal address pointer will automatically
increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the

beginning (wrap-around) of the address space. Once the
data from address location 1FFFFFH has been read, the
next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.

[Image: SST_I.jpg]

High-Speed-Read (50 MHz)
The High-Speed-Read instruction supporting up to 50 MHz
Read is initiated by executing an 8-bit command, 0BH, followed
by address bits [A23-A0] and a dummy byte. CE#
must remain active low for the duration of the High-Speed-
Read cycle. See Figure 5 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruction
outputs the data starting from the specified address
location. The data output stream is continuous through all

addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically increment
until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wraparound)
of the address space. Once the data from address
location FFFFFH has been read, the next output will be
from address location 00000H.

[Image: SST_J.jpg]

Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a protected
memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-

Program instruction is initiated by executing an 8-bit command,
02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 6 for the
Byte-Program sequence.

[Image: SST_K.jpg]

Auto Address Increment (AAI) Word-Program
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total programming
time when multiple bytes or entire memory array is to
be programmed. An AAI Word program instruction pointing
to a protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when initiating
an AAI Word Program operation. While within AAI
Word Programming sequence, the only valid instructions
are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users
have three options to determine the completion of each
AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY
bit in the software status register or wait TBP. Refer to End-
Of-Write Detection section for details.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI Word Program
instruction is initiated by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data is input sequentially, each one
from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0)
will be programmed into the initial address [A23-A1] with
A0=0, the second byte of Data (D1) will be programmed
into the initial address [A23-A1] with A0=1. CE# must be
driven high before the AAI Word Program instruction is executed.
The user must check the BUSY status before entering
the next valid command. Once the device indicates it is
no longer busy, data for the next two sequential addresses
may be programmed and so on. When the last desired
byte had been entered, check the busy status using the
hardware method or the RDSR instruction and execute the
Write-Disable (WRDI) instruction, 04H, to terminate AAI.
User must check busy status after WRDI to determine if the
device is ready for any command. See Figures 9 and 10 for
AAI Word programming sequence.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0) and the AAI bit (AAI=0).
End-of-Write Detection
There are three methods to determine completion of a program
cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection
by polling the BUSY bit in the Software Status Register or
wait TBP. The hardware end-of-write detection method is
described in the section below.

Hardware End-of-Write Detection
The hardware end-of-write detection method eliminates the
overhead of polling the Busy bit in the Software Status
Register during an AAI Word program operation. The 8-bit
command, 70H, configures the Serial Output (SO) pin to
indicate Flash Busy status during AAI Word programming.
(see Figure 7) The 8-bit command, 70H, must be executed
prior to executing an AAI Word-Program instruction. Once
an internal programming operation begins, asserting CE#
will immediately drive the status of the internal flash status
on the SO pin. A “0” indicates the device is busy and a “1”
indicates the device is ready for the next instruction. Deasserting
CE# will return the SO pin to tri-state.
The 8-bit command, 80H, disables the Serial Output (SO)
pin to output busy status during AAI-Word-program operation
and return SO pin to output Software Status Register
data during AAI Word programming. (see Figure 8)

[Image: SST_L.jpg]

[Image: SST_M.jpg]

[Image: SST_N.jpg]

4-KByte Sector-Erase
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Sector-Erase instruction is
initiated by executing an 8-bit command, 20H, followed by
address bits [A23-A0]. Address bits [AMS-A12] (AMS=Most

Significant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is executed.
The user may poll the Busy bit in the software status register
or wait TSE for the completion of the internal self-timed
Sector-Erase cycle. See Figure 11 for the Sector-Erase
sequence.

[Image: SST_O.jpg]

32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte Block-
Erase instruction is initiated by executing an 8-bit command,
52H, followed by address bits [A23-A0]. Address bits
[AMS-A15] (AMS = Most Significant Address) are used to

determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The 64-Kbyte Block-Erase instruction is initiated
by executing an 8-bit command D8H, followed by
address bits [A23-A0]. Address bits [AMS-A15] are used to
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The user may poll the Busy bit in the software
status register or wait TBE for the completion of the internal
self-timed 32-KByte Block-Erase or 64-KByte Block-Erase
cycles. See Figures 12 and 13 for the 32-KByte Block-
Erase and 64-KByte Block-Erase sequences.

[Image: SST_P.jpg]

Chip-Erase
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. The Chip-Erase instruction is initiated

by executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. The user may
poll the Busy bit in the software status register or wait TCE
for the completion of the internal self-timed Chip-Erase
cycle. See Figure 14 for the Chip-Erase sequence.

[Image: SST_Q.jpg]

Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction allows reading
of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.

CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. Read-
Status-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 15 for the RDSR instruction sequence.

[Image: SST_R.jpg]

Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit in the Status Register to 1 allowing Write
operations to occur. The WREN instruction must be executed
prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of

the Write-Status-Register (WRSR) instruction; however,
the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.

[Image: SST_S.jpg]

Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-
Enable-Latch bit and AAI bit to 0 disabling any new Write
operations from occurring. The WRDI instruction will not
terminate any programming operation in progress. Any program
operation in progress may continue up to TBP after
executing the WRDI instruction. CE# must be driven high
before the WRDI instruction is executed.

[Image: SST_T.jpg]

Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-Status-
Register instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruction
followed by the WRSR instruction works like SDP (software
data protection) command structure which prevents
any accidental alteration of the status register values. CE#
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.

Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status register.
CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
18 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”. When
the WP# is low, the BPL bit can only be set from “0” to “1” to
lock-down the status register, but cannot be reset from “1”
to “0”. When WP# is high, the lock-down function of the
BPL bit is disabled and the BPL, BP0, and BP1 and BP2
bits in the status register can all be changed. As long as
BPL bit is set to 0 or WP# pin is driven high (VIH) prior to the
low-to-high transition of the CE# pin at the end of the
WRSR instruction, the bits in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0, BP1, and
BP2 bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.

[Image: SST_U.jpg]

JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
SST25VF080B and the manufacturer as SST. The device
information can be read from executing the 8-bit command,
9FH. Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, BFH, is output from the device. After
that, a 16-bit device ID is shifted out on the SO pin. Byte 1,
BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies
the memory type as SPI Serial Flash. Byte 3, 8EH,
identifies the device as SST25VF080B. The instruction
sequence is shown in Figure 19. The JEDEC Read ID
instruction is terminated by a low to high transition on CE#
at any time during data output.

[Image: SST_V.jpg]

Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
SST25VF080B and manufacturer as SST. This command
is backward compatible to all SST25xFxxxA devices and
should be used as default device identification when multiple
versions of SPI Serial Flash devices are used in a
design. The device information can be read from executing
an 8-bit command, 90H or ABH, followed by address bits
[A23-A0]. Following the Read-ID instruction, the manufacturer’s
ID is located in address 00000H and the device ID is
located in address 00001H. Once the device is in Read-ID
mode, the manufacturer’s and device ID output data toggles
between address 00000H and 00001H until terminated
by a low to high transition on CE#.
Refer to Tables 6 and 7 for device identification data.

[Image: SST_W.jpg]

[Image: SST_X.jpg]

[Image: SST_Y.jpg]

[Image: SST_Z.jpg]

[Image: SST_0.jpg]

[Image: SST_1.jpg]

[Image: SST_2.jpg]

[Image: SST_3.jpg]

[Image: SST_4.jpg]

[Image: SST_5.jpg]

[Image: SST_6.jpg]

[Image: SST_7.jpg]

[Image: SST_8.jpg]

SST25VF080B.PDF

Driver sources
SOIC
WSON
SST25VF080B.txt
www find
quote


Forum Jump:


Users browsing this thread: 1 Guest(s)