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[Done] GA-5AX patch injection for RAS Precharge Time and Internal Tag RAM
#1
Smile 
Hello everybody Smile

Do you optimize the BIOS of old mainboards, too?

I've got an old Gigabyte GA-5AX (Rev 5.2) Super Socket 7 board with ALi Aladdin V chipset (Rev H). This latest chipset revision has a working internal Tag RAM. However, unlike other manufactures (e.g. Asus, Jetway) using chipset revision G, Gigabyte didn't enable it. Instead, they continued using a slower external Tag RAM.

I tried to enable internal Tag RAM during running OS sessions without success: changing operation mode of L2 Cache using TweakBIOS or WPCRedit resulted in instant reboot i.e. disabling/enabling L2 cache completely (whereas that can be done in BIOS-Setup without any trouble), enabling internal TAG RAM, or disabling external Tag RAM.

Therefore, I like to try enabling internal Tag RAM during POST by changing some register settings of the northbridge. To do so, I read "BIOS Disassembly Ninjutsu Uncovered" by Darmawan Salihun and adapted his mem-optimize patch to my purpose.
However, as this is the first time I'm writing a computer programme I'm not sure whether it's free from error.
Moreover, injecting it into the BIOS binary file, finding the POST jump table, and creating a jump instruction to the patch there turned out to be a too difficult task for me Huh

Please, can you help me injecting and executing a patch that enables the internal Tag RAM of my motherboard's chipset?

At first, as a proof of concept that the method works, I like to inject a patch that sets RAS Precharge Time (tRP) to 2T.
Normally, tRP is 3T at FSB 100 MHz. However, it can be lowered to 2T during running OS session using TweakBIOS or WPCRedit without any trouble.

If this works then I would just replace the first patch by a second one that tries to enable internal Tag RAM additionally.

These are the two patches (based on Darmawan Salihun's memory optimization) I wrote in FASM 1.73.12 (Windows version):
- tRP.ASM patches only memory timing
- TAG-tRP.ASM patches both Tag RAM and memory timing

The BIOS 5AXSOMOD.F42 I'm currently using is a patched version of Gigabyte's latest BIOS F4.
It was patched using BIOS Patcher 6.00.alpha_15 from www.ROM.by.
In addition, some hidden options were revealed with modbin.

It would be great if this version could be used for injection. You can find all files
- patched BIOS "5AXSOMOD.F42"
- patch protocol "readme.txt"
- first patch "tRP.ASM"
- binary file of first patch "tRP.BIN"
- second patch "TAG-tRP.ASM"
- binary file of second patch "TAG-tRP.BIN"
attached to this post
.zip   ModBIOSF42.zip (Size: 115.9 KB / Downloads: 5)

If the patched BIOS file is not suitable, Gigabyte's GA-5AX original BIOS F4 is also appreciated:
https://www.gigabyte.com/de/Motherboard/...support-dl

Datasheets of ALi Aladdin V Chipset:
Northbridge: http://www.hard-net.de/info_wissen/chips...-M1542.pdf
Southbridge: http://www.hard-net.de/info_wissen/chips...M1543C.pdf

Any help is welcome Shy !

Kind regards,
Lotosdrache
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#2
So, here I am again having a big smile in my face Big Grin

I finished the injection on Thursday. What was so difficult in June was so easy now 8 month later Smile  Pinczakko's guides here just gave me so much information that I could not see the forest for the trees Rolleyes
Sadly, the minor patch for lowering RAS Precharge Time that looked to be so easy didn't work. It seems the register is locked or the value is overwritten by code executed later. I have to study the datasheet again for this Undecided
The much more important patch for switching from external to internal Tag RAM on my Gigabyte GA-5AX Rev 5.2 with Aladdin V chipset Revision H, however, works flawlessly Big Grin

This was the configuration before with Gigabyte's BIOS version GA-5AX F4: [Image: 03biosf4k6-2400mitl3kwij1p.jpg]
As you can see:
- Secondary Cache (L2) = 512 KByte, direct mapped
- Cacheable Area L2  = 128 MByte < main memory!!

And now, with BIOS version F5 Powered by Lotosdrache Wink  : [Image: 11biosf5k6-2400mitl3o2qjyi.jpg]
- Secondary Cache (L2) = 512 KByte, direct mapped
- Cacheable Area L2  = 512 MByte, no noncacheable areas found Tongue

Tests were performed with AMD K6-2/400AFQ (CXT core) having no own internal L2 cache and 512 MiB RAM in total.
Latest experiments to make the patch switchable in the BIOS-Setup failed and indicated that the values from the setup aren't loaded at all at the moment the patch is executed. So, may be I can remove those lines from the code that backup/restore BIOS-Setup settings.

Note, this is not a performance update and was never thought to be one. It's just a functional update for techies Angel


Acknowledgment
Darmawan M S a.k.a Pinczakko, Thanks a million for your great guides! I read them several times and didin't unterstand 1% of the experiences you have collected and written down there Wink Nevertheless, they gave me all the information I needed Cool
Thanks a lot also to Mr. Scott from overclockers.com for providing me with the PCR files! Cool
Last but not least, Thanks to Skalabala from vogons.org for bringing me back to this board at the right time just when I was relaxed enough to see the forest for the trees again! Smile
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#3
Congratulation, if i want this, i'm doing it.
Quote:I finished the injection
So final mod 5AXSOMOD.F42 will be later?
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#4
(02-25-2020, 02:43 AM)LLC Wrote: Congratulation, if i want this, i'm doing it.
Quote:I finished the injection
So final mod 5AXSOMOD.F42 will be later?

Thanks!

There will be a final mod of the BIOS as soon as I finished optimisation.

I also like to try changing some other settings of the northbridge. For that purpose, it would be helpful to have a screenshot of the Asus P5A Rev. 1.04 and Rev. 1.06 settings as shown by WPCRedit 1.4 like here:
[Image: registerswpcredit10b9krkcm.png]

So, if anyone here owns that board in one of these revisions, please take time for this shoot.
Smile
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#5
Btw, the old sshot with Jetway J-542C you would be take on bios 542cD06.BIN, after "Load Setup Defaults" only(?, settings), i mean that 0x40 = 43h.
   
Some other info.
   
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#6
I've got a Jetway 542C of my own. Nevertheless, Thanks for the screenshot! Ours are identical or did you show me my own one? Wink

The screenshot I showed you above was taken from GA-5AX with old Gigabyte BIOS F4 one year ago when I started this project. That's why Offset 40 is still 13h. I was just too lazy to take a new one for this inquiry Wink
I know Award BIOS Editor and modbin and the Chipset Register they show. However, both programmes don't show everything. Moreover, not all of the offsets shown by Asus are also visible at Gigabyte's BIOS F4 and I don't know how to add additional ones.
https://www.overclockers.com/forums/show...harge-Time Rolleyes


Yesterday, I got a screenshot of Asus P5A Rev 1.04 and it was very informative:
Asus set tRP=2T by default what I also wanted to do but the GA-5AX didn't allow. I assumed this has something to do with Offset 72 bits 7 and 6 (SDRAM 100 MHz timing select) and it seems that I am on a good way: Gigabyte set both to 0 but Asus to 1. Let's see if I can change this...

Still missing: Sad
- WPCRedit 1.4 schreenshot of Asus P5A Rev. 1.06
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#7
Quote:but the GA-5AX didn't allow. I assumed this has something to do with

Try analyze code at address 0xE97B2-0xE97C1 (offset 0x97B2 of file original.tmp from 5AXSOMOD.F42), then upper.
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#8
Thank you very much for your help. Smile
As I am an absolut newbie in this way of working with PCs, it will take me some time to understand the code there. Please be patient with me.
Maybe you can give me some hints what happens at this point?
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#9
It's set 0x48 reg bus pci, read old - logic OR,bits - write new. Simple way try correct replace OR instruction on MOV and NOPs and check result.
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